1. Field of the Invention
The present invention relates to a light transmission equipment, and in particular to a clock change circuit used for a light transmission equipment for realizing a concatenation of synchronous transfer signals (STS) used in a synchronous transmission mode (STM).
In a recent light transmission equipment, a data communication technique such as the Internet or the like is required for enhancing a working efficiency of a single signal shared with many people. Also, a transmission function of STS-48 (2.4 Gb/s) data by the synchronous transmission mode for accommodating the Internet signal whose signal rate is improving is required for the improvement of services.
2. Description of the Related Art
The above-mentioned STS-48 data have a frame format as shown in FIG. 8, and a system diagram in which a light signal transmission is performed by using such STS-48 data is shown in FIG. 9.
Such a light transmission system forms a 4F-BLSR (4 Fiber-Bidirectional Line Switched Ring) system where stations A-D respectively forming a light transmission equipment are mutually connected with four optical fibers.
The STS-48 (2.4 Gb/s) data flow through each of the four optical fibers, which are shown by solid lines used as work or active lines (WK) and by dotted lines used as protect or standby lines (PT).
A prior art arrangement (1) of each station (light transmission equipment) in such a light transmission system is shown in FIG. 10.
In this arrangement, a circuit board is divided into two, i.e. a SHELF1 for the work line and a SHELF2 for the protect line. In the circuit board SHELF1, as for the station C in FIG. 9 for instance, data are to be inputted from the work line (WK) and the protect line (PT) on the EAST side where the side of the station D is made the EAST (East side) and the side of the station B is made the WEST (West side). By a connection switch in the middle, the data are to be outputted to the work line (WK) and the protect line (PT) on the same EAST side.
This applies to the WEST side in the circuit board SHELF2. As a matter of course, by the connection switch, it is made possible to input the data from the work line (WK) and the protect line (PT) on the EAST side of the circuit board SHELF1 and to output the data to the work line (WK) and the protect line (PT) on the WEST side of the circuit board SHELF2. Conversely it is made possible to input the data from the work line (WK) and the protect line (PT) on the WEST side of the circuit board SHELF2 and to output the data to the work line (WK) and the protect line (PT) on the EAST side of the circuit board SHELF1.
To be more specific, the circuit board SHELF1 is provided with a receiving portion OR1 for the work line (WK) and a receiving portion OR2 for the protect line (PT), which are respectively connected to demultiplexing portions DMUX1 and DMUX2.
In addition, the circuit board SHELF2 is provided with receiving portions OR3 and OR4 for the work line (WK) and the protect line (PT) from the WEST side, which are respectively connected to demultiplexing portions DMUX3 and DMUX4.
Since each of the lines transmits the STS-48 data, 1-48CH data flow through a single optical fiber, while at the demultiplexing portions DMUX1-4 the data are divided into data of 24 channels (hereinafter occasionally abbreviated as CH""s) to be bundled. Then, from the demultiplexing portion DMUX1 for instance, 1-24CH data are provided to the EAST side of an add/drop portion ADM1 which forms an add/drop portion ADM, and 1-24CH data from the demultiplexing portion DMUX2 are similarly provided to the EAST side of the add/drop portion ADM1.
Furthermore, 1-24CH data from the demultiplexing portion DMUX3 and 1-24CH data from the demultiplexing portion DMUX4 are inputted to the WEST side of the add/drop portion ADM1.
Also, at an add/drop portion ADM2, 25-48CH data from the demultiplexing portion DMUX1 and 25-48CH data from the demultiplexing portion DMUX2 are inputted to the EAST side, and 25-48CH data from the demultiplexing portion DMUX3 and 25-48CH data from the demultiplexing portion DMUX4 are inputted to the WEST side.
It is to be noted that add/drop portions ADM3 and ADM4 are provided as physical spare add/drop portions for the above-mentioned add/drop portions ADM1 and ADM2.
Also, the WEST side of the add/drop portion ADM1 outputs data bundles of 24CH""s, one of which is provided to a multiplexing portion MUX3 of the circuit board SHELF2 and the other of which is provided to a multiplexing portion MUX4 of same.
Furthermore, the EAST side of the add/drop portion ADM1 outputs data bundles of 24CH""s, one of which is provided to a multiplexing portion MUX1 of the circuit board SHELF1 and the other of which is provided to a multiplexing portion MUX2 of same.
At the add/drop portion ADM2, the output data on the WEST side are divided into data bundles of 25-48CH, one of which is provided to the multiplexing portion MUX3 and the other of which is provided to the multiplexing portion MUX4. Furthermore, one of the 25-48CH output data on the EAST side are provided to the multiplexing portion MUX1, and the other of the 25-48CH output data are provided to the multiplexing portion MUX2.
Then, the data of the multiplexing portions MUX1-4 respectively pass through transmitting portions OT1-OT4 to be outputted to the work line (WK) and the protect lines (PT) on the EAST and the WEST side.
A prior art arrangement of each add/drop portion ADM is shown in FIG. 11, in which line data on the EAST and the WEST side are provided to a span switch S-SW with 24CH data being divided into data bundles of 12CH""s on the work line and the protect line.
The span switch S-SW, as shown in FIG. 11, switches over the work line (WK) and the protect line (PT) based on a control signal (not shown), and a ring switch R-SW is provided next to the span switch S-SW to perform the switching operation opposite to the span switch S-SW.
The data which pass through the ring switch R-SW are provided to clock change circuits CSC1 and CSC2, in which a clock change from a line side to an equipment side is performed to output the data of 48CH""s.
The output data of the clock change circuits CSC1 and CSC2 are provided to a selector SEL through time slot assignment portions TSA1 and TSA2, where the data on either the EAST or the WEST side are to be dropped or branched to the equipment side.
In addition, the data from the equipment side are provided to service selectors SS1 and SS2 through time slot assignment portions TSA3 and TSA4. The 48CH data from the clock change circuits CSC1 and CSC2 are also provided to the service selectors SS1 and SS2.
Accordingly, either the line side or the equipment side is preliminarily selected, whereby the data divided into the data bundles of 12CH""s are sent to a ring bridge circuit R-Br. After performing the switching operation just opposite to the ring switch R-SW at the ring bridge circuit R-Br, the switching operation just opposite to the span switch S-SW is performed at a span bridge circuit S-Br, so that the data bundles of 12CH""s are respectively outputted as the line data on the WEST and the EAST side.
The above-mentioned example refers to the case where the 48CH (2.4 Gb/s) data are transmitted through a single optical fiber, while the case where STS-192 data are transmitted can be similarly considered as shown by parentheses in FIG. 10.
In this case, however, since 1-192CH data are divided at the demultiplexing portions DMUX1-DMUX4, not two but eight add/drop portions ADM are required for each circuit board. Also in this case, each of the add/drop portions has the arrangement shown in FIG. 11.
While the four optical fibers are used in the above-mentioned example, the case where two optical fibers (2F-BLSR) are used can be similarly considered as shown in FIG. 12.
Namely, the 48CH data from the EAST side are divided into data bundles of 24CH""s through the receiving portion OR1 and the demultiplexing portion DMUX1, so that at an add/drop portion ADM10 the 24CH data are inputted to both of the EAST and the WEST side for the work line and the protect line in the same way as the add/drop portion ADM1 shown in FIG. 10.
It is to be noted that an add/drop portion ADM20 is prepared for a physical spare in the same way as the add/drop portions ADM3 and ADM4 shown in FIG. 10, and the same data as the add/drop portion ADM10 are to be inputted and outputted.
When the STS-192 data are flowed as mentioned above in the light transmission system using such two optical fibers, a half of the 192CH""s, i.e. 1-96CH are assigned to the work line (WK) and 97-192CH are assigned to the protect line (PT).
For this reason, as shown in FIG. 13, with regard to the 24CH data demultiplexed by and outputted from the demultiplexing portion DMUX1, the data of 1-24CH are provided to the EAST side of the add/drop portion ADM10 for the work line, the data of 97-120CH are inputted to the EAST side for the protect line, the data of 25-48CH are provided to the EAST side of the add/drop portion ADM20 as the work data, and the data of 121-144CH are similarly provided to the EAST side as the protect data.
Finally, the ADM10 and ADM20 are to be provided by eight in all including those for the work line and for the protect line.
Also in such a 2-fiber system, the add/drop portion ADM shown in FIG. 11 adds or drops the data every 12CH and outputs them again to the line.
At the above-mentioned add/drop portion ADM in each of the light transmission systems, as shown in FIG. 11, each of the 24CH data is separately processed at the clock change circuits CSC1 and CSC2 as mentioned above. Since this process is based on the concatenation standard per STS-12C, there is no problem.
Namely, although a synchronous processing appears to be performed to the STS-48 data at a time, actually a data processing has been performed at a transmission rate (600 Mb/s) by the STS-12 standard.
Thus, there has been a problem that even the STS-48 data cannot be treated as concatenation standard signals of STS-48C so that a processing rate is suppressed to the transmission rate of the STS-12C.
It is accordingly an object of the present invention to provide a light transmission equipment, especially a clock change circuit, which can generate a desired concatenation signal from the maximum concatenation signal standardized in a synchronous transmission mode.
(1) In order to achieve the above-mentioned object, a light transmission equipment according to the present invention, comprising; a master and a slave circuit for clock change respectively inputting at least first and second line data based on a maximum transmission rate prescribed in a concatenation standard of a synchronous transmission mode obtained by dividing a desired transmission rate not prescribed in the concatenation standard, the clock change of the slave circuit being controlled whereby in-equipment data of the desired transmission rate is formed at both output data of the master and the slave circuit based on control information from the master circuit.
Namely, in the present invention, as the line data respectively inputted to the master and the slave circuit for the clock change, the data of the maximum transmission rate prescribed in the concatenation standard of the synchronous transmission mode obtained by dividing the desired transmission rate not prescribed in the concatenation standard are used.
The master circuit provides the control information for the synchronization of the clock change operation to the slave circuit whereby both output data of at least the master circuit and the slave circuit can produce the in-equipment data of the desired transmission rate not prescribed in the concatenation standard as the concatenation signal.
(2) The desired transmission rate may comprise STS-48. As the first and the second line data, data for 24 channels bundled with data of STS-12C (concatenation) standard may be respectively used.
Namely, only the standards up to the STS-12C (concatenation) standard are admitted at present. However, if the data of the STS-12C (concatenation) standard are bundled to perform a mutual concatenation, it becomes substantially equivalent to that STS-48C (concatenation) has been realized.
(3) Also, the above-mentioned master and slave circuits may respectively include pointer processors, and the pointer processor of the master circuit may assign the control information to that of the slave circuit.
Namely in the present invention, the pointer processor of the master circuit assigns the above-mentioned control information to the pointer processor of the slave circuit, so that the slave circuit can calculate a write address/read address based on the control information to perform a stuff control for the clock change.
(4) Also, the above-mentioned control information may include a pointer value and a write address on a line side, as well as stuff information and a read address on an equipment side.
(5) Furthermore, the above-mentioned master circuit may have a circuit for performing a parallel/serial conversion to the control information, and the slave circuit may have a circuit for performing a serial/parallel conversion to the control information.
Thus, it becomes possible to transfer various control information with a single signal line.
(6) Furthermore, the above-mentioned master circuit may have a circuit for performing a parity calculation to the control information, and the slave circuit may have a circuit for performing a parity check to the control information.
Thus, even if data multiplexed by a single signal line have much information, the transfer can be guaranteed by performing the parity calculation to the monitor.
(7) Furthermore, the above-mentioned slave circuit may have a circuit for delaying the second line data only for a time required for transferring the control information from the master circuit to the slave circuit, and the master circuit may have a circuit for delaying output data only for a time lag between the output data of the master circuit and the slave circuit.
Namely, since a predetermined time interval is required to transfer the control information, it is preferable to delay the data for the time and match the timings of the output data between the master and the slave circuit.